The End of the Microchip

(This essay appeared in a shorter version as a Nov. 4 op-ed in the Wall Street Journal.)

This is manifestly the microchip era.

It is the central controlling unit imparting functional intelligence to nearly every machine on the planet. It now promises a new industrial revolution bringing artificial intelligence (AI) to almost every human activity.

Fresh from dazzling the District of Columbia with the first GTC (Graphics Processing Unit [GPU] Technology Conference) in Washington, Oct. 27-29, the era’s epitome is Nvidia (NVDA) of Santa Clara, California. Now the world’s most valuable company, the Santa Clara microchip colossus, commands a market cap of over $5 trillion, selling millions of these epochal little devices for some $30,000 apiece.

The epitome of Nvidia is founder-CEO Jensen Huang, whose keynote combined a 3-D video phantasmagoria with an hour and forty minutes of technical exposition of the amazing advances wrought by his company’s chips. Climaxing his address was a celebration of Nvidia’s successes in bringing chip fabrication back to the United States from Taiwan and Korea. He thanked Donald Trump and proclaimed that the President was “Making America Great Again” through new energy policies that enable domestic AI microchip production.

Encapsulated in plastic, evocative perhaps of little ants or beetles, and with copper wires for legs, Nvidia’s latest chips bear designs with as many as 208 billion transistor switches. In a pivotal inversion, these chips no longer act independently like the central processing unit (CPU) in your laptop. Instead, enmeshed by the thousands and even the millions in vast data centers, they function as a single hyperscale computer.

The world’s supreme data center is Colossus 2 in Memphis. Center of Elon Musk’s xAI, source for Grok and self-driving cars, it integrates an estimated 1 million Nvidia chips in one vast computer. Known as GPUs for their history in graphics processing for game machines, these devices now parade in massively parallel formations, performing miracles of Generative Processing for AI’s more creative roles.

The “chip” has so captivated the minds of our time that even the revolutionary producers of new devices — and the marketing teams for my newsletters on “the end of chips”— insist on designating its potential successor as a “giant chip” or huge new chip or “superchip.” But the new device is, in fact, the opposite of the microchip. It dispenses with all the features that define its “chip-ness”— such as separate processing units or memories in plastic packages with wire “legs.” The new technology will wreak obsolescence on most computer systems linking chips to one another across printed circuit boards.

As is conveyed by Nvidia’s invasion of Washington, D.C., the microchip is not a mere technological phenomenon. The U.S. government regards chips so vital and strategic that the last three presidents and their respective administrations have endowed a $200 billion “Chips Act” industrial policy to support chip fabrication in the United States and keep it away from China.

Microchips now shape our foreign and national security policies from the Netherlands (home of the No. 1 maker of chip fabrication tools, ASML) to Taiwan and its prodigious TSMC (Taiwan Semiconductor Manufacturing Company, once — believe it or not—Texas Instruments). TSMC is the world’s primary fabricator of leading-edge chips, commanding a market share of over 95% of devices with features below 10 nanometers (billionths of meters) in size.

The effort to keep the crucial wafer-fabrication tools out of the hands of China, home of the vast majority of semiconductor engineers, is transforming the industry’s supply chains. Cutting off the Chinese market, industrial policies for chips have burdened U.S. producers of wafer-fab equipment without denting China’s ascent as an equipment manufacturer. Since these protectionist policies were adopted, the Chinese annual semiconductor capital equipment production has been growing by 30-40%, while the United States has been growing at an annual rate of 10%.

This change echoes the impact of the U.S. ban of Chinese leader Huawei’s equipment. Since Huawei was excluded from the United States, the Chinese company’s global market share of telecom equipment has risen from 32% in 2018 to 34% in 2024. The chief effect of the Huawei ban has been to lower U.S. sales to the company by $33 billion between 2021 and 2024.

Industrial policies and protectionism nearly always favor incumbent industries faced with obsolescence. In this respect, the Chips Act and related bans and tariffs are no different from previous mandates and subsidies for ethanol in gasoline, sugar cane in Louisiana, or rare earth mining of metals that now can be cheaply harvested from electronic waste by a company called Metallium in Houston. All these governmental actions to retrieve microchip production for the United States come in the face of clear portents of the end of microchips.

The signs are manifest in the exquisite physics of the crucial machine that both defines and limits the size and density of chips. Some of us call it the “Extreme Machine.” Made in Einhoven in the Netherlands by ASML—the world’s No. 1 producer of wafer-fab equipment by sales and centrality—the latest version of the machine performs what is called High Numerical Aperture Extreme Ultraviolet Lithography (HNA-EUV). If you are not Chinese, you can buy one for some $380 million. Some 44 have been sold so far. It comes in some 250 crates and requires some six months to install by hundreds of specialized engineers. It is, as IBM technical Vice President Dario Gil declared, “the world’s most complicated machine.”

The “Extreme Machine” and its precursors make it possible to inscribe coherent circuit patterns with some 200 billion “gate-all-around” 3D transistors in the latest Nvidia chips. Extreme Machine also makes possible the intricate mazes of microchips integrated in hyperscale Gigawatt AI data centers, such as Musk’s Memphis Colossus 2.

The Extreme Machine is, in essence, a kind of camera. It projects patterns of light on what might be termed the “films,” or “photoresists,” on the surface of silicon wafers. For much of last century’s history of the microchip, the features imprinted on the film were defined by the scale of the wavelengths or “colors” of visible light—between 700 nanometers (billionths of a meter) for red and 400 nanometers for violet. But these visible wavelengths are way out of date in today’s nanoscale chip environment, in which features on leading edge chips can be as small as 2 nanometers.

Hence, to imprint the infinitesimal patterns on chips, the machine contrives extreme ultraviolet beams, entirely invisible, from combinations of lasers. It projects the beams on what is termed the “die” (one unpackaged chip on a silicon wafer) through an intricately engineered quartz and chrome photomask bearing the chip design. Called a “reticle,” the photomask channels the laser beams onto hundreds of die, one at a time, on each 12-inch wafer. The process is called “stepping” or “scanning” the design across the wafer.

Governing everything that happens in the Extreme Machine is a convergence of physical laws and engineering constraints summed up as the “reticle limit.” The reticle defines the size of chips, and chip size in turn defines the granularity of AI computation. Thus, the reticle limit determines how many GPUs, mostly from Nvidia, must be linked to perform some AI task. Beyond a certain point, roughly 800 square millimeters (or 1.25 square inches), the iron laws of light and lightspeed prohibit larger designs.

The designs thus must be limited to current chip size. Imagine the effects of excessively enlarging a photograph; it becomes dim or blurred. Similar dimness or imprecision will doom any chip. The ASML machine is for chip fabrication both a miracle worker and the “Achilles’ keel,” which keeps the entire system aligned but imperils its yields in the coming storm.

As more extreme ultra-violet light is used with predicted wavelengths in the angstroms (10ths of nanometers), the possible chip size becomes smaller even as the circuitry grows denser. This development has prompted a move toward smaller more specialized chips called “chiplets” that are plugged onto the backs of larger chips to relieve them of particular functions, such as access to ever-multiplying layers of high-bandwidth-memory connections and optical links.

You can see the effects of the reticle limit in the ever-mounting complexity and heterogeneity of Nvidia-defined vast hyperscale datacenters. The division of AI labor into smaller chips and increasing layers of 3D contraptions entails ever more complex overall systems. The result of breaking the computation down into smaller chips and “chiplets”, each with its own elaborate packaging, is a greater need for ultimate re-integration of the processes to yield coherent outcomes. The calculation has to be first dispersed among multiple chips, then re-compiled.

Nvidia’s proprietary method is called NVLink, with a long software tail called CUDA (computer unified device architecture) that represents the prescribed path into the datacenter’s awesome chip resources. CUDA, plus the expense of fabricating datacenter GPU chips, has made Nvidia a virtual monopoly. Its method for contriving packages for an ever more diverse set of multifold functions through “interposer” communications layers is called CoWoS (chip on wafer on substrate). This is an intricate packaging scheme that enables extension of the chip model into future generations.

The effect is more communications overhead between chips, requiring ever more complex packages, ever more wires and fiber optic links, ever more transceivers translating optics to electronics and back, and SERDES convertors between serial one bit at a time transmissions for short links over copper and parallel or deserialized links for longer optical connections across the datacenter. All these layers of solutions come in the context of ever larger data centers costing gigadollars to build and using collective terawatts of power.

It is ironic to notice that the alleged test of the capabilities of these vast power gorging multi-ton contraptions is human brains that weigh 3 pounds and run on 12 to 14 watts. All eight billion of us do not use the wattage of a handful of hyperscale data centers. The huge dimensions and expense of the overall AI machine, with its roots in the Extreme Machine, are what prompts AI prophets to make ever more extreme and apocalyptic claims.

As a result of the inexorable reticle limit, all this is now approaching its end. Although yet to be fully grasped by the industry, the reticle limit ultimately portends the end of chips.

On the way is a wafer-scale integration model. Rather than inscribing hundreds of chip designs across a 12-inch wafer and then “scribing” or cutting them into separate “die” to be encapsulated in plastic packages as chips, the design spreads across the entire 12-inch wafer.

Already pioneered by Elon Musk in his Dojo computer for Tesla (now spun out to DensityAI), the wafer-scale concept has enabled Cerebras, of Palo Alto, to eschew chips entirely. Cerebras’s WSE-3 (wafer scale engine), now boasts some 4 trillion transistors, 14 times more than Nvidia’s Blackwell, with 7,000 times more memory bandwidth. Achieved through inscribing the memory directly on the wafer rather than relegating it to distant chips and chiplets in high-bandwidth memory mazes.

Now contriving a full wafer scale future is David Lam, the legendary founder of wafer fab equipment titan Lam Research (LAMR), the third-largest wafer fab equipment firm. Founding Multibeam Corporation, Lam has contrived a massively parallel e-beam machine, called Multi-Column E-Beam Lithography (MEBL). Bypassing the reticle limit, it has already demonstrated the capability of inscribing eight-inch wafers. It is on a viable path to future inscription of industry standard 12-inch wafers. Look Ma, no Chips! No China! (Or even Taiwan). No elaborate packaging in the Philippines or Shenzhen. No NVIDIA CoWoS 3-D packaging kludges.

The technique is direct-write, with no photomasks or reticles and thus no reticle limit. The previous problem of e-beam direct write was its exponentially slower process compared to ASML’s ultraviolet patterning through masks. This slowness of e-beam was what ordained its use in writing reticles that then could be used to inscribe chips millions of times faster through masks. But this obstacle has been mostly overcome through the massively parallel e-beam writing architecture.

The functionality of the Lam device has been demonstrated for customers of SkyWater semiconductor of Bloomington, Minnesota, with a new eight-inch fab in Austin, Texas. SkyWater is now coming into its own through its Multibeam deal, increasing Pentagon contracts, and governmental kudos as a U.S.-based chip fabrication company.

We are entering a post-microchip era. It would be unfortunate if it happens first in China, where wafer-scale is also being pursued by venture capitalists.

George Gilder’s COSM Conference will be held Nov. 19-21 in Scottsdale, Arizona.